Information

46.4.7.6 Receive FIFO Overflow Interrupt Request
The Receive FIFO Overflow Request indicates that an overflow condition in the RX
FIFO has occurred. A Receive FIFO Overflow request is generated when RX FIFO and
shift register are full and a transfer is initiated. The RFOF_RE bit in the RSER must be
set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the MCR, the data from the transfer that
generated the overflow is either ignored or shifted in to the shift register. If the ROOE bit
is set, the incoming data is shifted in to the shift register. If the ROOE bit is cleared, the
incoming data is ignored.
46.4.8 Power Saving Features
The DSPI supports following power-saving strategies:
• External Stop mode
• Module Disable mode - Clock gating of non-memory mapped logic
46.4.8.1 Stop Mode (External Stop Mode)
The DSPI supports the stop mode protocol. When a request is made to enter external stop
mode, the DSPI block acknowledges the request . If a serial transfer is in progress, the
DSPI waits until it reaches the frame boundary before it is ready to have its clocks shut
off .While the clocks are shut off, the DSPI memory-mapped logic is not accessible. The
states of the interrupt and DMA request signals cannot be changed while in External Stop
mode.
46.4.8.2 Module Disable Mode
Module disable mode is a block-specific mode that the DSPI can enter to save power.
Host CPU can initiate the module disable mode by setting the MDIS bit in the MCR. The
module disable mode can also be initiated by hardware. A power management block can
initiate the module disable mode by asserting the DOZE mode signal while the DOZE bit
in the MCR is set.
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1249