Information

When the MDIS bit is set or the DOZE mode signal is asserted while the DOZE bit is set,
the DSPI negates Clock Enable signal at the next frame boundary. If implemented, the
Clock Enable signal can stop the clock to the non-memory mapped logic. When Clock
Enable is negated, the DSPI is in a dormant state, but the memory mapped registers are
still accessible. Certain read or write operations have a different effect when the DSPI is
in the module disable mode. Reading the RX FIFO Pop Register does not change the
state of the RX FIFO. Likewise, writing to the TX FIFO Push Register does not change
the state of the TX FIFO. Clearing either of the FIFOs has no effect in the module disable
mode. Changes to the DIS_TXF and DIS_RXF fields of the MCR have no effect in the
module disable mode. In the module disable mode, all status bits and register flags in the
DSPI return the correct values when read, but writing to them has no effect. Writing to
the TCR during module disable mode has no effect. Interrupt and DMA request signals
cannot be cleared while in the module disable mode.
46.5 Initialization/Application Information
This section describes how to initialize the DSPI module.
46.5.1 How to Manage DSPI Queues
The queues are not part of the DSPI, but the DSPI includes features in support of queue
management. Queues are primarily supported in SPI Configuration.
1. When DSPI executes last command word from a queue, the EOQ bit in the command
word is set to indicate to the DSPI that this is the last entry in the queue.
2. At the end of the transfer, corresponding to the command word with EOQ set is
sampled, the EOQ flag (EOQF) in the SR is set.
3. The setting of the EOQF flag disables serial transmission and reception of data,
putting the DSPI in the STOPPED state. The TXRXS bit is cleared to indicate the
STOPPED state.
4. The DMA can continue to fill TX FIFO until it is full or step 5 occurs.
5. Disable DSPI DMA transfers by disabling the DMA enable request for the DMA
channel assigned to TX FIFO and RX FIFO. This is done by clearing the
corresponding DMA enable request bits in the DMA Controller.
6. Ensure all received data in RX FIFO has been transferred to memory receive queue
by reading the RXCNT in SR or by checking RFDF in the SR after each read
operation of the POPR.
Initialization/Application Information
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1250 Freescale Semiconductor, Inc.