Information

7. Modify DMA descriptor of TX and RX channels for new queues
8. Flush TX FIFO by writing a '1' to the CLR_TXF bit in the MCR. Flush RX FIFO by
writing a '1' to the CLR_RXF bit in the MCR.
9. Clear transfer count either by setting CTCNT bit in the command word of the first
entry in the new queue or via CPU writing directly to SPI_TCNT field in the TCR.
10. Enable DMA channel by enabling the DMA enable request for the DMA channel
assigned to the DSPI TX FIFO, and RX FIFO by setting the corresponding DMA set
enable request bit.
11. Enable serial transmission and serial reception of data by clearing the EOQF bit.
46.5.2 Switching Master and Slave Mode
When changing modes in the DSPI, follow the steps below to guarantee proper operation.
1. Halt the DSPI by setting MCR[HALT].
2. Clear the transmit and receive FIFOs by writing a 1 to the CLR_TXF and CLR_RXF
bits in MCR.
3. Set the appropriate mode in MCR[MSTR] and enable the DSPI by clearing
MCR[HALT].
46.5.3 Baud Rate Settings
The following table shows the baud rate that is generated based on the combination of the
baud rate prescaler PBR and the baud rate scaler BR in the CTAR registers. The values
calculated assume a 100 MHz system frequency and the double baud rate DBR bit is
clear.
NOTE
The clock frequency mentioned above is given as an example in
this chapter. Refer to the clocking chapter for the frequency
used to drive this module in the device.
Chapter 46 SPI (DSPI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1251