Information

Table 47-41. I2C Divider and Hold Values (continued)
ICR
(hex)
SCL
Divider
SDA Hold
Value
SCL Hold
(Start)
Value
SCL Hold
(Stop)
Value
ICR
(hex)
SCL
Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(Start)
Value
SCL Hold
(Stop)
Value
19 96 9 46 49 39 1536 129 766 769
1A 112 17 54 57 3A 1792 257 894 897
1B 128 17 62 65 3B 2048 257 1022 1025
1C 144 25 70 73 3C 2304 385 1150 1153
1D 160 25 78 81 3D 2560 385 1278 1281
1E 192 33 94 97 3E 3072 513 1534 1537
1F 240 33 118 121 3F 3840 513 1918 1921
47.4.2 10-bit Address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte.
Various combinations of read/write formats are possible within a transfer that includes
10-bit addressing.
47.4.2.1 Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed. When a 10-bit address follows a START condition,
each slave compares the first seven bits of the first byte of the slave address (11110XX)
with its own address and tests whether the eighth bit (R/W direction bit) is 0. It is
possible that more than one device finds a match and generates an acknowledge (A1).
Each slave that finds a match compares the eight bits of the second byte of the slave
address with its own address, but only one slave finds a match and generate an
acknowledge (A2). The matching slave remains addressed by the master until it receives
a STOP condition (P) or a repeated START condition (Sr) followed by a different slave
address.
Table 47-42. Master-Transmitter Addresses Slave-Receiver with a 10-bit
Address
S
Slave
addres
s first 7
bits
11110
+
AD10
+ AD9
R/W
0
A1
Slave
addres
s
second
byte
AD[8:1]
A2 Data A ... Data A/A P
Chapter 47 Inter-Integrated Circuit (I2C)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1277