Information

gtb_in
FTM1
GTBEEN = 1
FTM Counter
CONF Register
GTBEOUT = 0
FTM0
GTBEEN = 1
FTM Counter
CONF Register
GTBEOUT = 1
gtb_out
gtb_in
gtb_in
FTM2
GTBEEN = 1
FTM Counter
CONF Register
GTBEOUT = 0
Figure 3-43. FTM Global Time Base Configuration
3.8.2.10 FTM BDM and debug halt mode
In the FTM chapter, references to the chip being in "BDM" are the same as the chip being
in “debug halt mode".
3.8.3 PIT Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Register
access
Peripheral
bridge
Periodic interrupt
timer
Figure 3-44. PIT configuration
Table 3-55. Reference links to related information
Topic Related module Reference
Full description PIT PIT
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Timers
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
128 Freescale Semiconductor, Inc.