Information

48.3.3 UART Control Register 1 (UARTx_C1)
This read/write register controls various optional features of the UART system.
Addresses: UART0_C1 is 4006_A000h base + 2h offset = 4006_A002h
UART1_C1 is 4006_B000h base + 2h offset = 4006_B002h
UART2_C1 is 4006_C000h base + 2h offset = 4006_C002h
UART3_C1 is 4006_D000h base + 2h offset = 4006_D002h
Bit 7 6 5 4 3 2 1 0
Read
LOOPS UARTSWAI RSRC M WAKE ILT PE PT
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C1 field descriptions
Field Description
7
LOOPS
Loop Mode Select
When LOOPS is set, the RxD pin is disconnected from the UART and the transmitter output is internally
connected to the receiver input.The transmitter and the receiver must be enabled to use the loop function.
0 Normal operation.
1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is
determined by the RSRC bit.
6
UARTSWAI
UART Stops in Wait Mode
0 UART clock continues to run in wait mode.
1 UART clock freezes while CPU is in wait mode.
5
RSRC
Receiver Source Select
This bit has no meaning or effect unless the LOOPS bit is set. When LOOPS is set, the RSRC bit
determines the source for the receiver shift register input.
0 Selects internal loop back mode and receiver input is internally connected to transmitter output.
1 Single-wire UART mode where the receiver input is connected to the transmit pin input signal.
4
M
9-bit or 8-bit Mode Select
This bit must be set when 7816E is set/enabled.
0 Normal - start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
1 Use - start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
3
WAKE
Receiver Wakeup Method Select
WAKE determines which condition wakes the UART: address mark in the most significant bit position of a
received data character or an idle condition on the receive pin input signal.
0 Idle-line wakeup.
1 Address-mark wakeup.
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1302 Freescale Semiconductor, Inc.