Information

UARTx_S1 field descriptions (continued)
Field Description
0
PF
Parity Error Flag
PF is set when PE is set, S2[LBKDE] is disabled, and the parity of the received data does not match its
parity bit. The PF is not set in the case of an overrun condition. When the PF bit is set it only indicates that
a dataword was received with parity error since the last time it was cleared. There is no guarantee that the
first dataword read from the receive buffer has a parity error or that there is only one dataword in the
buffer that was received with a parity error unless the receive buffer was a depth of one. To clear PF, read
S1 and then read the UART data register (D). Within the receive buffer structure the received dataword is
tagged if it was received with a parity error. That information is available by reading the ED register prior
to reading the D register.
0 No parity error has been detected since the last time this flag was cleared. If the receive buffer has a
depth greater than 1 then there may be data in the receive buffer what was received with a parity
error.
1 At least one dataword was received with a parity error since the last time this flag was cleared.
48.3.6 UART Status Register 2 (UARTx_S2)
The S2 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. Also, this register can be polled by the MCU to check the status of these bits.
This register can be read or written at any time, with the exception of the MSBF and
RXINV bits which should only be changed by the user between transmit and receive
packets.
Addresses: UART0_S2 is 4006_A000h base + 5h offset = 4006_A005h
UART1_S2 is 4006_B000h base + 5h offset = 4006_B005h
UART2_S2 is 4006_C000h base + 5h offset = 4006_C005h
UART3_S2 is 4006_D000h base + 5h offset = 4006_D005h
Bit 7 6 5 4 3 2 1 0
Read
LBKDIF RXEDGIF MSBF RXINV RWUID BRK13 LBKDE
RAF
Write
Reset
0 0 0 0 0 0 0 0
UARTx_S2 field descriptions
Field Description
7
LBKDIF
LIN Break Detect Interrupt Flag
LBKDIF is set when LBKDE is set and a LIN break character is detected, when 11 consecutive logic 0s (if
C1[M] = 0) or 12 consecutive logic 0s (if C1[M] = 1) appear on the receiver input. LBKDIF is set right after
receiving the last LIN break character bit. LBKDIF is cleared by writing a 1 to it.
0 No LIN break character has been detected.
1 LIN break character has been detected.
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1308 Freescale Semiconductor, Inc.