Information
UARTx_S2 field descriptions (continued)
Field Description
LBKDE selects a longer break character detection length. While LBKDE is set, the S1[RDRF], S1[NF],
S1[FE], and S1[PF] flags are prevented from setting. When LBKDE is set, see Overrun operation. The
LBKDE bit must be cleared when C7816[ISO7816E] is set.
0 Break character is detected at length of 10 bit times (C1[M] = 0), 11 (C1[M] = 1 and C4[M10] = 0), or
12 (C1[M] = 1, C4[M10] = 1, and S1[PE] = 1).
1 Break character is detected at length of 11 bits times (if C1[M] = 0 or 12 bits time (if C1[M] = 1).
0
RAF
Receiver Active Flag
RAF is set when the UART receiver detects a logic 0 during the RT1 time period of the start bit search.
RAF is cleared when the receiver detects an idle character when C7816[ISO7816E] is cleared/disabled.
When C7816[ISO7816E] is enabled the RAF is cleared if the C7816[TTYPE] = 0 expires or the
C7816[TTYPE] = 1 expires.
NOTE: In the case when C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible to configure the
guard time to be 12. However, in the event that a NACK is required to be transmitted the data
transfer actually takes 13 ETU with the 13th ETU slot being a inactive buffer. Hence in this
situation the RAF may deassert one ETU prior to actually being inactive.
0 UART receiver idle/inactive waiting for a start bit.
1 UART receiver active (RxD input not idle).
48.3.7 UART Control Register 3 (UARTx_C3)
Writing to R8 bit does not have any effect. The TXDIR and TXINV bits can only be
changed between transmit and receive packets.
Addresses: UART0_C3 is 4006_A000h base + 6h offset = 4006_A006h
UART1_C3 is 4006_B000h base + 6h offset = 4006_B006h
UART2_C3 is 4006_C000h base + 6h offset = 4006_C006h
UART3_C3 is 4006_D000h base + 6h offset = 4006_D006h
Bit 7 6 5 4 3 2 1 0
Read R8
T8 TXDIR TXINV ORIE NEIE FEIE PEIE
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C3 field descriptions
Field Description
7
R8
Received Bit 8
R8 is the ninth data bit received when the UART is configured for 9-bit data format (C1[M] = 1) or
(C4[M10] = 1).
6
T8
Transmit Bit 8
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1310 Freescale Semiconductor, Inc.