Information

UARTx_C5 field descriptions (continued)
Field Description
NOTE: If C2[TIE] and TDMAS are both set, then C2[TCIE] must be cleared, and D register must not be
written outside of servicing of a DMA request.
0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request
interrupt service.
1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a
DMA transfer.
6
Reserved
This read-only field is reserved and always has the value zero.
5
RDMAS
Receiver Full DMA Select
RDMAS configures the receiver data register full flag, S1[RDRF], to generate interrupt or DMA requests if
C2[RIE] is set.
NOTE: If C2[RIE] is cleared, the RDRF DMA and RDFR interrupt request signals are not asserted when
the S1[RDRF] flag is set, regardless of the state of RDMAS.
0 If C2[RIE] is set and the S1[RDRF] flag is set, the RDFR interrupt request signal is asserted to
request interrupt service.
1 If C2[RIE] is set and the S1[RDRF] flag is set, the RDRF DMA request signal is asserted to request a
DMA transfer.
4–0
Reserved
This read-only field is reserved and always has the value zero.
48.3.13 UART Extended Data Register (UARTx_ED)
This register contains additional information flags that are stored with a received
dataword. This register may be read at any time but only contains valid data if there is a
dataword in the receive FIFO.
NOTE
The data contained in this register represents additional
information regarding the conditions on which a dataword was
received. The importance of this data varies with application,
and in some cases maybe completely optional. These fields
automatically update to reflect the conditions of the next
dataword whenever D is read.
NOTE
If the S1[NF] and S1[PF] flags have not been set since the last
time the receive buffer was empty, the NOISY and PARITYE
bits will be zero.
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1316 Freescale Semiconductor, Inc.