Information

UARTx_CFIFO field descriptions
Field Description
7
TXFLUSH
Transmit FIFO/Buffer Flush
Writing to this bit causes all data that is stored in the transmit FIFO/buffer to be flushed. This does not
affect data that is in the transmit shift register.
0 No flush operation occurs.
1 All data in the transmit FIFO/Buffer is cleared out.
6
RXFLUSH
Receive FIFO/Buffer Flush
Writing to this bit causes all data that is stored in the receive FIFO/buffer to be flushed. This does not
affect data that is in the receive shift register.
0 No flush operation occurs.
1 All data in the receive FIFO/buffer is cleared out.
5–2
Reserved
This read-only field is reserved and always has the value zero.
1
TXOFE
Transmit FIFO Overflow Interrupt Enable
When this bit is set the TXOF flag will generate an interrupt to the host.
0 TXOF flag does not generate an interrupt to the host.
1 TXOF flag generates an interrupt to the host.
0
RXUFE
Receive FIFO Underflow Interrupt Enable
When this bit is set the RXUF flag will generate an interrupt to the host.
0 RXUF flag does not generate an interrupt to the host.
1 RXUF flag generates an interrupt to the host.
48.3.18 UART FIFO Status Register (UARTx_SFIFO)
This register provides various status information regarding the transmit and receiver
buffers/FIFOs, including interrupt information. This register may be written or read at
anytime.
Addresses: UART0_SFIFO is 4006_A000h base + 12h offset = 4006_A012h
UART1_SFIFO is 4006_B000h base + 12h offset = 4006_B012h
UART2_SFIFO is 4006_C000h base + 12h offset = 4006_C012h
UART3_SFIFO is 4006_D000h base + 12h offset = 4006_D012h
Bit 7 6 5 4 3 2 1 0
Read TXEMPT RXEMPT 0
TXOF RXUF
Write
Reset
1 1 0 0 0 0 0 0
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1322 Freescale Semiconductor, Inc.