Information

UARTx_TCFIFO field descriptions
Field Description
7–0
TXCOUNT
Transmit Counter
The value in this register indicates the number of datawords that are in the transmit buffer/FIFO. If a
dataword is in the process of being transmitted (i.e. in the transmit shift register) it is not included in the
count. This value may be used in conjunction with the PFIFO[TXFIFOSIZE] field to calculate how much
room is left in the transmit buffer/FIFO.
48.3.21 UART FIFO Receive Watermark (UARTx_RWFIFO)
This register provides the ability to set a programmable threshold for notification of
needing to remove data from the receiver buffer/FIFO. This register may be read at any
time but should only be written when C2[RE] is not asserted. Changing the value in this
register will not clear the S1[RDRF] flag.
Addresses: UART0_RWFIFO is 4006_A000h base + 15h offset = 4006_A015h
UART1_RWFIFO is 4006_B000h base + 15h offset = 4006_B015h
UART2_RWFIFO is 4006_C000h base + 15h offset = 4006_C015h
UART3_RWFIFO is 4006_D000h base + 15h offset = 4006_D015h
Bit 7 6 5 4 3 2 1 0
Read
RXWATER
Write
Reset
0 0 0 0 0 0 0 1
UARTx_RWFIFO field descriptions
Field Description
7–0
RXWATER
Receive Watermark
When the number of datawords in the Receive FIFO/buffer is equal to or greater than the value in this
register field the event is flagged. An interrupt via S1[RDRF] or a DMA request via C5[RDMAS] will be
generated as determined by C5[RDMAS] and C2[RIE] fields. For proper operation the value in the
RXWATER field must be set to be less than the size of the Receive buffer/FIFO size as indicated by
PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and greater than 0.
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1325