Information

Communication interfaces
3.9.1 Universal Serial Bus (USB) Subsystem
The USB subsystem includes these components:
• Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS)
device or FS/LS host. The module complies with the USB 2.0 specification.
• USB transceiver that includes internal 15 kΩ pulldowns on the D+ and D- lines for
host mode functionality.
• A 3.3 V regulator.
• USB device charger detection module.
• VBUS detect signal: To detect a valid VBUS in device mode, use a GPIO signal that
can wake the chip in all power modes.
USB controller
FS/LS
transceiver
USB voltage
regulator
D+ D-
VREGIN
Device charger
detect
VOUT33
Figure 3-48. USB Subsystem Overview
3.9.1.1 USB Wakeup
When the USB detects that there is no activity on the USB bus for more than 3 ms, the
INT_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the
appropriate action.
Waking from a low power mode (except in LLS/VLLS mode where USB is not powered)
occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting
the USBTRC0[USBRESMEN] bit enables this function.
3.9.1.2 USB Power Distribution
This chip includes an internal 5 V to 3.3 V USB regulator that powers the USB
transceiver or the MCU (depending on the application).
3.9
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 133