Information

48.4 Functional description
This section provides a complete functional description of the UART block.
The UART allows full duplex, asynchronous, NRZ serial communication between the
CPU and remote devices, including other CPUs. The UART transmitter and receiver
operate independently, although they use the same baud rate generator. The CPU
monitors the status of the UART, writes the data to be transmitted, and processes
received data.
48.4.1 Transmitter
SHIFT DIRECTION
PARITY
GENERATION
PE
PT
TRANSMITTER CONTROL
M
MSBF
INTERNAL BUS
Tx port en
Tx input buffer en
Tx output buffer en
STOP
TXINV
TxD Pin Control
START
BAUDRATE GENERATE
MODULE
CLOCK
SBR12:0
BRFA4:0
VARIABLE 12-BIT TRANSMIT
SHIFT REGISTER
M10
R485 CONTROL
RTS_B
CTS_B
TXDIR
SBK
TE
DMA Done
7816 LOGIC
TxD
IRQ / DMA
LOGIC
INFRARED LOGIC
DMA Requests
IRQ Requests
TxD
LOOP
CONTROL
LOOPS
RSRC
UART DATA REGISTER (UART_D)
Figure 48-156. Transmitter Block Diagram
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1335