Information

When C7816[ISO_7816E] = 1 setting the C2[TE] bit does not result in a preamble being
generated. The transmitter starts transmitting as soon as the corresponding guard time
expires. When C7816[TTYPE] = 0 the value in GT is used, when C7816[TTYPE] = 1 the
value BGT is used since it is assumed that the C2[TE] will remain asserted until the end
of the block transfer. The C2[TE] bit is automatically cleared when in C7816[TTYPE] =
1 and the block being transmitted has been completed. When C7816[TTYPE] = 0, the
transmitter listens for a NACK indication. If no NACK is received it is assumed that
character was correctly received. If a NACK is received the transmitter will resend the
data, assuming that the number of retries for that character (number of NACKs received)
is less than or equal to the value in ET7816[TXTHRESHOLD].
Hardware supports odd or even parity. When parity is enabled, the bit immediately
preceding the stop bit is the parity bit.
When the transmit shift register is not transmitting a frame, the transmit data output
signal goes to the idle condition, logic 1. If at any time software clears the C2[TE] bit, the
transmitter enable signal goes low and the transmit signal goes idle.
If software clears C2[TE] while a transmission is in progress, the character in the transmit
shift register continues to shift out, provided S1[TC] flag was cleared during the data
write sequence. To clear the S1[TC] flag, the S1 register must be read followed by a write
to UARTx_D register.
If the S1[TC] flag is cleared during character transmission and the C2[TE] bit is cleared,
the transmission enable signal is deasserted at the completion of current frame. Following
this, the transmit data out signal enters the idle state even if there is data pending in the
UART transmit data buffer. To ensure that all the data written in the FIFO is transmitted
on the link before clearing C2[TE], wait for the S1[TC] flag to set. Alternatively, the
same can be achieved by setting TWFIFO[TXWATER] to 0x0 and waiting for
S1[TDRE] to set.
48.4.1.4 Transmitting break characters
Setting the C2[SBK] loads the transmit shift register with a break character. A break
character contains all logic 0s and has no start, stop, or parity bit. Break character length
depends on the C1[M] and C1[PE] bits, the S2[BRK13] bit, and the C4[M10] bit. Refer
to the following table.
Table 48-163. Transmit break character length
S2[BRK13] C1[M] C4[M10] C1[PE] Bits transmitted
0 0 — — 10
Table continues on the next page...
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1337