Information

Table 48-163. Transmit break character length (continued)
S2[BRK13] C1[M] C4[M10] C1[PE] Bits transmitted
0 1 0 — 11
0 1 1 0 11
0 1 1 1 12
1 0 — — 13
1 1 — — 14
As long as C2[SBK] is set, transmitter logic continuously loads break characters into the
transmit shift register. After software clears the C2[SBK] bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The automatic
logic 1 at the end of a break character guarantees the recognition of the start bit of the
next character. Break bits are not supported when C7816[ISO_7816E] is set/enabled.
NOTE
When queuing a break character, it will be transmitted
following the completion of the data value currently being
shifted out from the shift register. This means that if data is
queued in the data buffer to be transmitted, the break character
will preempt that queued data. The queued data will then be
transmitted after the break character is complete.
48.4.1.5 Idle characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character
length depends on the C1[M] and C1[PE] bits and the C4[M10] bit. The preamble is a
synchronizing idle character that begins the first transmission initiated after setting the
C2[TE] bit. When C7816[ISO_7816E] is set/enabled, idle characters are not sent or
detected. When data is not being transmitted the data I/O line is in an inactive state.
If the C2[TE] bit is cleared during a transmission, the transmit data output signal
becomes idle after completion of the transmission in progress. Clearing and then setting
the C2[TE] bit during a transmission queues an idle character to be sent after the
dataword currently being transmitted.
Note
When queuing an idle character the idle character will be
transmitted following the completion of the data value currently
being shifted out from the shift register. This means that if data
Functional description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1338 Freescale Semiconductor, Inc.