Information

• After every start bit.
• After the receiver detects a data bit change from logic 1 to logic 0 (after the majority
of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of
the next RT8, RT9, and RT10 samples returns a valid logic 0).
To locate the start bit, data recovery logic does an asynchronous search for a logic 0
preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT
clock begins to count to 16.
SAMPLES
Rx pin input
RT CLOCK
RT CLOCK COUNT
RESET RT CLOCK
1 1
1 1
0
START BIT
LSB
RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4
RT5
RT6
RT2 RT3 RT4
RT7 RT8 RT9
RT11
RT13 RT14 RT15 RT16
1
1
1
1
0
0
0 0 0 0
RT10
RT12
RT1
START BIT
QUALIFICATION
DATA
SAMPLING
START BIT
VERIFICATION
Figure 48-159. Receiver data sampling
To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5,
and RT7 when C7816[ISO_7816E] is cleared/disabled and RT8, RT9 and RT10 when
C7816[ISO_7816E] is set/enabled. The following table summarizes the results of the start
bit verification samples.
Table 48-164. Start bit verification
RT3, RT5, and RT7 samples
RT8, RT9, RT10 samples when 7816E
Start bit verification Noise flag
000 Yes 0
001 Yes 1
010 Yes 1
011 No 0
100 Yes 1
101 No 0
110 No 0
111 No 0
If start bit verification is not successful, the RT clock is reset and a new search for a start
bit begins.
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1343