Information

As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid
falling edge within the frame. Resynchronization within frames will correct a
misalignment between transmitter bit times and receiver bit times.
48.4.2.9.1 Slow data tolerance
The following figure shows how much a slow received frame can be misaligned without
causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1
but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
RECEIVER
RT CLOCK
MSB
STOP
DATA
SAMPLES
RT16
RT15 RT14 RT13 RT12
RT11 RT10
RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1
Figure 48-167. Slow data
For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles
(9 bit times × 16 RT cycles + 10 RT cycles).
With the misaligned character shown in the above figure, the receiver counts 154 RT
cycles at the point when the count of the transmitting device is 147 RT cycles (9 bit times
× 16 RT cycles + 3 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a slow 8-bit data character with no errors is:
((154 − 147) ÷ 154) × 100 = 4.54%
For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles
(10 bit times × 16 RT cycles + 10 RT cycles).
With the misaligned character shown in the above figure, the receiver counts 170 RT
cycles at the point when the count of the transmitting device is 163 RT cycles (10 bit
times × 16 RT cycles + 3 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a slow 9-bit character with no errors is:
((170 − 163) ÷ 170) × 100 = 4.12%
Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1351