Information

• MMC 4-bit
• MMC 8-bit
• CE-ATA 1-bit
• CE-ATA 4-bit
• CE-ATA 8-bit
• Identification mode (up to 400 kHz)
• MMC full speed mode (up to 20 MHz)
• MMC high speed mode (up to 52 MHz)
• SD/SDIO full speed mode (up to 25 MHz)
• SD/SDIO high speed mode (up to 50 MHz)
49.3 SDHC signal descriptions
Table 49-1. SDHC signal descriptions
Signal Description I/O
SDHC_DCLK Generated clock used to drive the
MMC, SD, SDIO or CE-ATA cards.
O
SDHC_CMD Send commands to and receive
responses from the card.
I/O
SDHC_D0 DAT0 line or busy-state detect I/O
SDHC_D1 8-bit mode: DAT1 line
4-bit mode: DAT1 line or interrupt
detect
1-bit mode: Interrupt detect
I/O
SDHC_D2 4-/8-bit mode: DAT2 line or read wait
1-bit mode: Read wait
I/O
SDHC_D3 4-/8-bit mode: DAT3 line or configured
as card detection pin
1-bit mode: May be configured as card
detection pin
I/O
SDHC_D4 DAT4 line in 8-bit mode
Not used in other modes
I/O
SDHC_D5 DAT5 line in 8-bit mode
Not used in other modes
I/O
Table continues on the next page...
Chapter 49 Secured digital host controller (SDHC)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1381