Information

3.9.2.3 Number of message buffers
Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes.
3.9.2.4 FlexCAN Clocking
3.9.2.4.1 Clocking Options
The FlexCAN module has a register bit CANCTRL[CLK_SRC] that selects between
clocking the FlexCAN from the internal bus clock or the input clock (EXTAL).
3.9.2.4.2 Clock Gating
The clock to each CAN module can be gated on and off using the SCGCn[CANx] bits.
These bits are cleared after any reset, which disables the clock to the corresponding
module. The appropriate clock enable bit should be set by software at the beginning of
the FlexCAN initialization routine to enable the module clock before attempting to
initialize any of the FlexCAN registers.
3.9.2.5 FlexCAN Interrupts
The FlexCAN has multiple sources of interrupt requests. However, some of these sources
are OR'd together to generate a single interrupt request. See below for the mapping of the
individual interrupt sources to the interrupt request:
Request Sources
Message buffer Message buffers 0-15
Bus off Bus off
Error • Bit1 error
• Bit0 error
• Acknowledge error
• Cyclic redundancy check (CRC) error
• Form error
• Stuffing error
• Transmit error warning
• Receive error warning
Transmit Warning Transmit Warning
Receive Warning Receive Warning
Wake-up Wake-up
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 139