Information

SDHC_PRSSTAT field descriptions (continued)
Field Description
During a write transaction, a block gap event interrupt is generated when this bit is changed to 0, as result
of the stop at block gap request being set. This status is useful for the host driver in determining when to
issue commands during write busy state.
0b No valid data
1b Transferring data
7
SDOFF
SD Clock Gated Off Internally
This status bit indicates that the SD clock is internally gated off, because of buffer over/under-run or read
pause without read wait assertion, or the driver has cleared SYSCTL[SDCLKEN] bit to stop the SD clock.
This bit is for the host driver to debug data transaction on the SD bus.
0b SD clock is active
1b SD clock is gated off
6
PEROFF
SDHC clock
Gated Off Internally
This status bit indicates that the SDHC clock is internally gated off. This bit is for the host driver to debug
transaction on the SD bus. When INITA bit is set, SDHC sending 80 clock cycles to the card, the
SDCLKEN bit must be ‘1’ to enable the output card clock, otherwise the
SDHC clock
will never be gate off, so
SDHC clock
and
bus clock
will be always active.
0b SDHC clock
is active
1b
SDHC clock
is gated off
5
HCKOFF
System Clock
Gated Off Internally
This status bit indicates that the system clock is internally gated off. This bit is for the host driver to debug
during a data transfer.
0b System clock
is active
1b
System clock
is gated off
4
IPGOFF
Bus Clock
Gated Off Internally
This status bit indicates that the bus clock is internally gated off. This bit is for the host driver to debug.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1396 Freescale Semiconductor, Inc.