Information

Address: SDHC_IRQSTAT is 400B_1000h base + 30h offset = 400B_1030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
DMAE
0
AC12E
0
DEBE
DCE
DTOE
CIE
CEBE
CCE
CTOE
W
w1c
w1c
w1c w1c w1c w1c w1c w1c w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CINT
CRM
CINS
BRR
BWR DINT
BGE TC CC
W
w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SDHC_IRQSTAT field descriptions
Field Description
31–29
Reserved
This read-only field is reserved and always has the value zero.
28
DMAE
DMA Error
Occurs when an Internal DMA transfer has failed. This bit is set to 1, when some error occurs in the data
transfer. This error can be caused by either Simple DMA or ADMA, depending on which DMA is in use.
The value in DMA System Address register is the next fetch address where the error occurs. Since any
error corrupts the whole data block, the host driver shall re-start the transfer from the corrupted block
boundary. The address of the block boundary can be calculated either from the current DSADDR value or
from the remaining number of blocks and the block size.
0b No Error
1b Error
27–25
Reserved
This read-only field is reserved and always has the value zero.
24
AC12E
Auto CMD12 Error
Occurs when detecting that one of the bits in the Auto CMD12 Error Status register has changed from 0 to
1. This bit is set to 1, not only when the errors in Auto CMD12 occur, but also when the Auto CMD12 is
not executed due to the previous command error.
0b No Error
1b Error
23
Reserved
This read-only field is reserved and always has the value zero.
22
DEBE
Data End Bit Error
Occurs either when detecting 0 at the end bit position of read data, which uses the DAT line, or at the end
bit position of the CRC.
Table continues on the next page...
Chapter 49 Secured digital host controller (SDHC)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1407