Information

49.4.14 Interrupt Status Enable Register (SDHC_IRQSTATEN)
Setting the bits in this register to 1 enables the corresponding interrupt status to be set by
the specified event. If any bit is cleared, the corresponding interrupt status bit is also
cleared (i.e. when the bit in this register is cleared, the corresponding bit in interrupt
status register is always 0).
NOTE
• Depending on PROCTL[IABG] bit setting, SDHC may be
programmed to sample the card interrupt signal during the
interrupt period and hold its value in the flip-flop. There
will be some delays on the card interrupt, asserted from the
card, to the time the host system is informed.
• To detect a CMD line conflict, the host driver must set both
IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to
1.
Address: SDHC_IRQSTATEN is 400B_1000h base + 34h offset = 400B_1034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
DMAESEN
0
AC12ESEN
0
DEBESEN
DCESEN
DTOESEN
CIESEN
CEBESEN
CCESEN
CTOESEN
W
Reset
0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CINTSEN
CRMSEN
CINSEN
BRRSEN
BWRSEN DINTSEN
BGESEN
TCSEN
CCSEN
W
Reset
0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1
SDHC_IRQSTATEN field descriptions
Field Description
31–29
Reserved
This read-only field is reserved and always has the value zero.
28
DMAESEN
DMA Error Status Enable
0b Masked
1b Enabled
27–25
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Chapter 49 Secured digital host controller (SDHC)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1411