Information

SDHC_IRQSTATEN field descriptions (continued)
Field Description
24
AC12ESEN
Auto CMD12 Error Status Enable
0b Masked
1b Enabled
23
Reserved
This read-only field is reserved and always has the value zero.
22
DEBESEN
Data End Bit Error Status Enable
0b Masked
1b Enabled
21
DCESEN
Data CRC Error Status Enable
0b Masked
1b Enabled
20
DTOESEN
Data Timeout Error Status Enable
0b Masked
1b Enabled
19
CIESEN
Command Index Error Status Enable
0b Masked
1b Enabled
18
CEBESEN
Command End Bit Error Status Enable
0b Masked
1b Enabled
17
CCESEN
Command CRC Error Status Enable
0b Masked
1b Enabled
16
CTOESEN
Command Timeout Error Status Enable
0b Masked
1b Enabled
15–9
Reserved
This read-only field is reserved and always has the value zero.
8
CINTSEN
Card Interrupt Status Enable
If this bit is set to 0, the SDHC will clear the interrupt request to the system. The card interrupt detection is
stopped when this bit is cleared and restarted when this bit is set to 1. The host driver should clear the
this bit before servicing the card interrupt and should set this bit again after all interrupt requests from the
card are cleared to prevent inadvertent interrupts.
0b Masked
1b Enabled
7
CRMSEN
Card Removal Status Enable
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1412 Freescale Semiconductor, Inc.