Information

SDHC_IRQSIGEN field descriptions (continued)
Field Description
0b Masked
1b Enabled
2
BGEIEN
Block Gap Event Interrupt Enable
0b Masked
1b Enabled
1
TCIEN
Transfer Complete Interrupt Enable
0b Masked
1b Enabled
0
CCIEN
Command Complete Interrupt Enable
0b Masked
1b Enabled
49.4.16 Auto CMD12 Error Status Register (SDHC_AC12ERR)
When the AC12ESEN bit in the Status register is set, the host driver shall check this
register to identify what kind of error the Auto CMD12 indicated. This register is valid
only when the Auto CMD12 Error status bit is set.
The following table shows the relationship between the Auto CMGD12 CRC error and
the Auto CMD12 command timeout error.
Table 49-25. Relationship Between Command CRC Error and Command Timeout Error for
Auto CMD12
Auto CMD12 CRC error Auto CMD12 timeout error Type of error
0 0 No error
0 1 Response timeout error
1 0 Response CRC error
1 1 CMD line conflict
Changes in Auto CMD12 Error Status register can be classified in three scenarios:
1. When the SDHC is going to issue an auto CMD12.
• Set bit 0 to 1 if the auto CMD12 can't be issued due to an error in the previous
command.
• Set bit 0 to 0 if the auto CMD12 is issued.
2. At the end bit of an auto CMD12 response.
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1416 Freescale Semiconductor, Inc.