Information

1. Standard features of all UARTs:
• RS-485 support
• Hardware flow control (RTS/CTS)
• 9-bit UART to support address mark with parity
• MSB/LSB configuration on data
2. UART0 and UART1 are clocked from the core clock, the remaining UARTs are
clocked on the bus clock. The maximum baud rate is 1/16 of related source clock
frequency.
3. IrDA is available on all UARTs
4. UART0 contains the standard features plus ISO7816
5. AMR support on all UARTs. The pin control and interrupts (PORT) module supports
open-drain for all I/O.
6. UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs
7. All other UARTs contain a 1-entry transmit and receive FIFOs
3.9.5.2 UART wakeup
The UART can be configured to generate an interrupt/wakeup on the first active edge that
it receives.
3.9.5.3 UART interrupts
The UART has multiple sources of interrupt requests. However, some of these sources
are OR'd together to generate a single interrupt request. See below for the mapping of the
individual interrupt sources to the interrupt request:
The status interrupt combines the following interrupt sources:
Source UART 0 UART 1 UART 2 UART 3
Transmit data empty x x x x
Transmit complete x x x x
Idle line x x x x
Receive data full x x x x
LIN break detect x x x x
RxD pin active edge x x x x
Initial character detect x — — —
The error interrupt combines the following interrupt sources:
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 145