Information

Source UART 0 UART 1 UART 2 UART 3
Receiver overrun x x x x
Noise flag x x x x
Framing error x x x x
Parity error x x x x
Transmitter buffer
overflow
x x x x
Receiver buffer
underflow
x x x x
Transmit threshold
(ISO7816)
x — — —
Receiver threshold
(ISO7816)
x — — —
Wait timer (ISO7816) x — — —
Character wait timer
(ISO7816)
x — — —
Block wait timer
(ISO7816)
x — — —
Guard time violation
(ISO7816)
x — — —
3.9.6 SDHC Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Crossbar switch
Register
access
Peripheral
bridge
Module signals
SDHC
Transfers
Signal multiplexing
Figure 3-59. SDHC configuration
Table 3-71. Reference links to related information
Topic Related module Reference
Full description SDHC SDHC
System memory map System memory map
Clocking Clock Distribution
Power management Power management
Table continues on the next page...
Communication interfaces
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
146 Freescale Semiconductor, Inc.