Information

Signal multiplexing

access

Peripheral

bridge

Module signals

I S

Figure 3-60. I

S configuration

Table 3-72. Reference links to related information

Topic Related module Reference

Full description I

S I2S

System memory map System memory map

Clocking Clock Distribution

Power management Power management

Signal multiplexing Port control Signal Multiplexing

NOTE

The I2S master clock can be output on the I2S0_MCLK pin or

input on the I2S0_CLKIN pin. Using the I2S0_RX_BCLK pin

to output the I2S master clock in synchronous mode is not

supported on this device.

3.9.7.1 Interrupts

The interrupt outputs from the I

S module are OR'd to create a single interrupt to the

interrupt control logic.

3.9.7.2 DMA requests

The I

S module has two DMA requests:

• Transmit FIFO

• Receive FIFO

Communication interfaces

K20 Sub-Family Reference Manual, Rev. 6, Nov 2011

148 Freescale Semiconductor, Inc.