Information

3.9.7.3 I
2
S clock generation
To generate the desired frequencies for the I
2
S module there are multiple clocking
options as shown below:
• The core/system clock is routed to an 8-bit fractional divider to generate the I
2
S
clock.
• The PLL output is routed to an 8-bit fractional divider to generate the I
2
S clock.
• The EXTAL pin directly drives the I
2
S clock.
• The I2S0_CLKIN pin directly drives the I
2
S clock.
These options are controlled by the SIM_SOPT2[I2SSRC] field, and the 8-bit fractional
divider is controlled by the SIM_CLKDIV2[I2SDIV, I2SFRAC] fields. See the SIM
module for details.
3.9.7.4 I
2
S operation in low power modes
The I
2
S module requires interaction with the rest of the system to move data in or out of
the FIFOs. Since the rest of the system is not active in stop, VLPS, and LLS modes, there
is no use for the I
2
S in these modes. The I
2
S is powered so that it retains state in these
modes, but it is not functional.
In VLPR and VLPW modes, the I
2
S is functional. However, the I
2
S is limited to 400 kHz
maximum frequency.
Human-machine interfaces (HMI)
3.10.1 GPIO configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
3.10
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 149