Information

STFS, SRFS
STXD
SRXD
8-bit Data
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
7
6
7
6
(not used in
gated clock)
Continuous
STCK, SRCK
Early
STFS, SRFS
Gated STCK
Bit-length frame sync
Word-length frame sync
Figure 50-3. Serial clock and frame sync timing
The following table shows a list of clock pin configurations.
Table 50-3. Clock pin configurations
CR
[SYN]
RCR TCR
SRCK STCK SRFS STFS
RXDIR RFDIR TXDIR TFDIR
Asynchronous Mode
0 0 0 0 0 RCK in TCK in RFS in TFS in
0 0 0 0 1 RCK in TCK in RFS in TFS out
0 0 1 0 0 RCK in TCK in RFS out TFS in
0 0 1 0 1 RCK in TCK in RFS out TFS out
0 0 0 1 0 RCK in TCK out RFS in TFS in
0 0 0 1 1 RCK in TCK out RFS in TFS out
0 0 1 1 0 RCK in TCK out RFS out TFS in
0 0 1 1 1 RCK in TCK out RFS out TFS out
0 1 0 0 0 RCK out TCK in RFS in TFS in
0 1 0 0 1 RCK out TCK in RFS in TFS out
0 1 1 0 0 RCK out TCK in RFS out TFS in
0 1 1 0 1 RCK out TCK in RFS out TFS out
Table continues on the next page...
I2S signal descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1492 Freescale Semiconductor, Inc.