Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 32-Bit 100 MHz I/O number 52

1491

50.3.1 I

S Transmit Data Registers 0 (I2Sx_TX0)

The TX0 registers store the data to be transmitted by the I2S.

Addresses: I2S0_TX0 is 4002_F000h base + 0h offset = 4002_F000h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TX0

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I2Sx_TX0 field descriptions

Field Description

31–0

TX0

I2S transmit data

S transmit data. These bits store the data to be transmitted by the I

S. These are implemented as the

first word of their respective Tx FIFOs. Data written to these registers transfers to the transmit shift

transfers from TX0 and TX1 to TXSR. TX1 can only be used in two-channel mode. Multiple writes to the

TX registers do not result in the previous data being over-written by the subsequent data. Instead they are

ignored. Protection from over-writing is present irrespective of whether the transmitter is enabled or not.

Example: If Tx FIFO0 is in use and you write Data1 - 16 to TX0, Data16 does not overwrite Data1. Data1 -

15 are stored in the FIFO while Data16 is discarded. Example: If Tx FIFO0 is not in use and you write

Data1, Data2 to TX0, then Data2 does not overwrite Data1 and is discarded.

NOTE: Enable I

S (CR[I2SEN]=1) before writing to the I

S transmit data registers.

50.3.2 I

S Transmit Data Registers 1 (I2Sx_TX1)

The TX1 registers store the data to be transmitted by the I2S.

Addresses: I2S0_TX1 is 4002_F000h base + 4h offset = 4002_F004h