Information
I2Sx_IER field descriptions (continued)
Field Description
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
22
RDMAE
Receive DMA Enable.
This bit allows I
2
S to request for DMA transfers. When enabled, DMA requests are generated when any of
the RFF0/1 bits in the ISR are set and if the corresponding RFEN bit is also set. If the corresponding FIFO
is disabled, a DMA request is generated when the corresponding RDR bit is set.
0 I
2
S receiver DMA requests disabled.
1 I
2
S receiver DMA requests enabled.
21
RIE
Receive Interrupt Enable.
This control bit allows the I
2
S to issue receiver related interrupts to the core.
0 I
2
S receiver interrupt requests disabled.
1 I
2
S receiver interrupt requests enabled.
20
TDMAE
Transmit DMA Enable.
This bit allows I
2
S to request for DMA transfers. When enabled, DMA requests are generated when any of
the ISR[TFE0/1] bits are set and if the corresponding TCR[TFEN] bit is also set. If the corresponding FIFO
is disabled, a DMA request is generated when the corresponding TDE bit is set.
0 I
2
S transmitter DMA requests disabled.
1 I
2
S transmitter DMA requests enabled.
19
TIE
Transmit Interrupt Enable.
This control bit allows the I
2
S to issue transmitter data related interrupts to the core.
0 I
2
S transmitter interrupt requests disabled.
1 I
2
S transmitter interrupt requests enabled.
18
CMDAUEN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
17
CMDDUEN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
16
RXTEN
Enable Bit.
Each bit controls whether the corresponding status bit in ISR can issue an interrupt to the core or not.
0 Corresponding status bit cannot issue interrupt.
1 Corresponding status bit can issue interrupt.
15
RDR1EN
Enable Bit.
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1506 Freescale Semiconductor, Inc.