Information
50.3.8 I
2
S Transmit Configuration Register (I2Sx_TCR)
The TCR directs the transmit operation of the I2S. A power-on reset clears all TCR bits.
However, I2S reset does not affect the TCR bits.
Addresses: I2S0_TCR is 4002_F000h base + 1Ch offset = 4002_F01Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TXBIT0
TFEN1
TFEN0
TFDIR
TXDIR
TSHFD
TSCKP
TFSI
TFSL
TEFS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
I2Sx_TCR field descriptions
Field Description
31–10
Reserved
This read-only field is reserved and always has the value zero.
9
TXBIT0
Transmit Bit 0.
This control bit allows I
2
S to transmit the data word from bit position 0 or 15/31 in the transmit shift
register. The shifting data direction can be MSB or LSB first, controlled by the TCR[TSHFD] bit.
0 Shifting with respect to bit 31 (if word length = 16, 18, 20, 22 or 24) or bit 15 (if word length = 8, 10 or
12) of transmit shift register (MSB aligned).
1 Shifting with respect to bit 0 of transmit shift register (LSB aligned).
8
TFEN1
Transmit FIFO Enable 1.
This bit enables transmit FIFO 1. When enabled, the FIFO allows 15 samples to be transmitted by the I
2
S
(per channel) (a 9th sample can be shifting out) before TDE1 bit is set. When the FIFO is disabled, an
interrupt is generated when a single sample is transferred to the transmit shift register (provided the
interrupt is enabled).
0 Transmit FIFO 1 disabled.
1 Transmit FIFO 1 enabled.
7
TFEN0
Transmit FIFO Enable 0.
This bit enables transmit FIFO 0. When enabled, the FIFO allows 15 samples to be transmitted by the I
2
S
per channel (a 9th sample can be shifting out) before TDE0 bit is set. When the FIFO is disabled, an
interrupt is generated when a single sample is transferred to the transmit shift register (provided the
interrupt is enabled).
0 Transmit FIFO 0 disabled.
1 Transmit FIFO 0 enabled.
6
TFDIR
Transmit Frame Direction.
This bit controls the direction and source of the transmit frame sync signal. Internally generated frame
sync signal is sent out through the STFS port and external frame sync is taken from the same port.
0 Frame sync is external.
1 Frame sync generated internally.
Table continues on the next page...
Chapter 50 Integrated interchip sound (I2S)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1509