Information

Table 3-75. TSI module functionality in MCU operation modes (continued)
MCU operation mode TSI clock sources TSI operation mode
when GENCS[TSIEN]
is 1
Functional electrode
pins
Required
GENCS[STPE] state
VLPS OSCERCLK Active mode All 1
LLS LPOCLK,
VLPOSCCLK
Low power mode Determined by
PEN[LPSP]
1
VLLS3 LPOCLK,
VLPOSCCLK
Low power mode Determined by
PEN[LPSP]
1
VLLS2 LPOCLK,
VLPOSCCLK
Low power mode Determined by
PEN[LPSP]
1
VLLS1 LPOCLK,
VLPOSCCLK
Low power mode Determined by
PEN[LPSP]
1
3.10.2.3 TSI clocks
This table shows the TSI clocks and the corresponding chip clocks.
Table 3-76. TSI clock connections
Module clock Chip clock
BUSCLK Bus clock
MCGIRCLK MCGIRCLK
OSCERCLK OSCERCLK
LPOCLK 1 kHz LPO clock
VLPOSCCLK ERCLK32K
3.10.2.4 TSI Interrupts
The TSI has multiple sources of interrupt requests. However, these sources are OR'd
together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI
status register to determine the exact interrupt source.
3.10.2.5 Shield drive signal
The shield drive signal is not supported on this device. Ignore this feature in the TSI
chapter.
Human-machine interfaces (HMI)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
152 Freescale Semiconductor, Inc.