Information

Table 50-50. I
2
S mode selection (continued)
CR[I2SMODE] Mode type
10 I
2
S slave mode
11 Normal mode
In normal (non-I
2
S) mode operation, no register bits are forced to any particular state
internally, and the user can program the I
2
S to work in any operating condition.
When I
2
S modes are entered (CR[I2SMODE] = 01 or 10), these settings are
recommended:
• Synchronous mode (CR[SYN] =1)
• Tx shift direction: msb transmitted first (TCR[TSHFD] = 0)
• Rx shift direction: msb received first (RCR[RSHFD] = 0)
• Tx data clocked at falling edge of the clock (TCR[TSCKP] = 1)
• Rx data latched at rising edge of the clock (RCR[RSCKP] = 1)
• Tx frame sync active low (TCR[TFSI] = 1)
• Rx frame sync active low (RCR[RFSI] = 1)
• Tx frame sync initiated one bit before data is transmitted (TCR[TEFS] = 1)
• Rx frame sync initiated one bit before data is received (RCR[REFS] = 1)
• Tx frame rate should be 2 (TCCR[DC] = 1)
• Rx frame rate should be 2 (RCCR[DC] = 1)
50.4.1.4.1 I
2
S master mode
In I
2
S master mode (CR[I2SMODE] = 01b), the following additional settings are
recommended:
• Internal generated bit clock (TCR[TXDIR] = 1)
• Internal generated frame sync (TCR[TFDIR] = 1)
The processor automatically performs these settings in I
2
S master mode:
• Network mode is selected (CR[NET] = 1)
• Tx frame sync length set to one-word-long-frame (TCR[TFSL]=0)
Chapter 50 Integrated interchip sound (I2S)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1539