Information

DC[4:0]
Frame
Sync
TFSL
Tx
Control
TFSI
STFS
Tx Frame Sync In
Word Clock
TFDIR(0=input)
Frame
TFDIR(1=output)
Tx Frame Sync Out
TFSI
Rate
Figure 50-57. I
2
S transmit frame sync generator block diagram
50.4.2.2 DIV2, PSR and PM bits description
The bit clock frequency can be calculated from the I
2
S serial system clock using
id-73884.
Note
You must ensure that the bit-clock frequency must be 5 times
the peripheral clock frequency. The oversampling clock
frequency can go up to peripheral clock frequency. Bits DIV2,
PSR and PM must not be cleared at the same time.
I S
2
From this, the frame clock frequency can be calculated:
Figure 50-58. I
2
S bit clock equation
For example, if the I
2
S oversampling clock (network clock) is 12.288 MHz, in 8-bit word
normal mode with DC = 1, PM = 47, PSR = 0, DIV2 = 1, a bit clock rate of 64 kHz is
generated. Since the 8-bit word rate is equal to one (i.e. normal mode), the sampling rate
(or frame sync rate) would then be 64/(1×8) = 8 kHz.
Functional description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1546 Freescale Semiconductor, Inc.