Information

Table 50-55. I
2
S transmit data interrupts (continued)
Interrupt TIE TUEn TFEn/TDEn
Transmit data 1 (without exception) 1 0 1
Transmit data 1 interrupts (n = 1)
Transmit data 0 (with exception status) 1 1 1
Transmit data 0 (without exception) 1 0 1
50.4.6 Internal frame and clock shutdown
During transmit/receive operation, clearing TE/RE stops data transmission/reception
when the current frame ends. If the CR[TFRCLKDIS, RFRCLKDIS] bit is set in the
current or previous frames, the I
2
S stops driving the frame sync and clock signals when
the current frame ends. After this, the TCRTFRC]] and TCR[RFRC] status bits are set to
indicate the frame completion state. If TE is cleared four clock cycles before the next
frame, an extra invalid frame is generated.
The following figure is an illustration of transmission case where:
• TCR[TXDIR] and TCR[TFDIR] are set
• CR[TE] is cleared
• CR[TFRCLKDIS] is set during the current or previous frame
CLK
FS
Tx data
CR[TE]
CR[TFRCLKDIS]
ISR[TFRC]
Figure 50-59. CR[TFRCLKDIS] assertion in current or previous frame as CR[TE] is
Disabled
If CR[TFRCLKDIS or RFRCLKDIS] bit is not set while CR[TE or RE] is cleared, the
I
2
S continues generating frame sync and clock signals (if direction is from the I
2
S), Upun
setting CR[TFRCLKDIS or RFRCLKDIS], the I
2
S stops driving these signals at the end
of the current frame. Following this, the TFRC/RFRC status bits are set to indicate the
frame completion state.
Functional description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1552 Freescale Semiconductor, Inc.