Information

4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory
maps
The peripheral memory map is accessible via two slave ports on the crossbar switch in
the 0x4000_0000–0x400F_FFFF region. The device implements two peripheral bridges
(AIPS-Lite 0 and 1):
• AIPS-Lite0 covers 512 KB
• AIPS-Lite1 covers 508 KB with 4 KB assigned to the general purpose input/output
module (GPIO)
AIPS-Lite0 is connected to crossbar switch slave port 2, and is accessible at locations
0x4000_0000–0x4007_FFFF.
AIPS-Lite1 and the general purpose input/output module share the connection to crossbar
switch slave port 3. The AIPS-Lite1 is accessible at locations 0x4008_0000–
0x400F_EFFF. The general purpose input/output module is accessible in a 4-kbyte region
at 0x400F_F000–0x400F_FFFF. Its direct connection to the crossbar switch provides
master access without incurring wait states associated with accesses via the AIPS-Lite
controllers.
Modules that are disabled via their clock gate control bits in the SIM registers disable the
associated AIPS slots. Access to any address within an unimplemented or disabled
peripheral bridge slot results in a transfer error termination.
For programming model accesses via the peripheral bridges, there is generally only a
small range within the 4 KB slots that is implemented. Accessing an address that is not
implemented in the peripheral results in a transfer error termination.
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
Table 4-2. Peripheral bridge 0 slot assignments
System 32-bit base address Slot
number
Module
0x4000_0000 0 Peripheral bridge 0 (AIPS-Lite 0)
0x4000_1000 1 —
0x4000_2000 2 —
0x4000_3000 3 —
0x4000_4000 4 Crossbar switch
0x4000_5000 5 —
Table continues on the next page...
Chapter 4 Memory Map
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 157