Information

TSI memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_5154 Channel n threshold register (TSI0_THRESHLD13) 32 R/W 0000_0000h
52.6.6/
1587
4004_5158 Channel n threshold register (TSI0_THRESHLD14) 32 R/W 0000_0000h
52.6.6/
1587
4004_515C Channel n threshold register (TSI0_THRESHLD15) 32 R/W 0000_0000h
52.6.6/
1587
52.6.1 General Control and Status Register (TSIx_GENCS)
All GENCS bits can be read at any time, but must not be written while GENCS[SCNIP]
is set.
Addresses: TSI0_GENCS is 4004_5000h base + 0h offset = 4004_5000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
0
LPCLKS
LPSCNITV NSCN PS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EOSF
OUTRGF
EXTERF
OVRF
0
SCNIP
TSIEN
TSIIE
ERIE
ESOR
Reserved Reserved
STM
STPE
W
w1c
w1c w1c
w1c
SWTS
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TSIx_GENCS field descriptions
Field Description
31
Reserved
Reserved
This field is reserved.
30–29
Reserved
This read-only field is reserved and always has the value zero.
28
LPCLKS
Low Power Mode Clock Source Selection
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1574 Freescale Semiconductor, Inc.