Information

Section Number Title Page
Chapter 20
Direct memory access multiplexer (DMAMUX)
20.1 Introduction...................................................................................................................................................................403
20.1.1 Overview......................................................................................................................................................403
20.1.2 Features........................................................................................................................................................404
20.1.3 Modes of operation......................................................................................................................................404
20.2 External signal description............................................................................................................................................405
20.3 Memory map/register definition...................................................................................................................................405
20.3.1 Channel Configuration Register (DMAMUX_CHCFGn)...........................................................................406
20.4 Functional description...................................................................................................................................................407
20.4.1 DMA channels with periodic triggering capability......................................................................................407
20.4.2 DMA channels with no triggering capability...............................................................................................410
20.4.3 "Always enabled" DMA sources.................................................................................................................410
20.5 Initialization/application information...........................................................................................................................411
20.5.1 Reset.............................................................................................................................................................411
20.5.2 Enabling and configuring sources................................................................................................................411
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................415
21.1.1 Block diagram..............................................................................................................................................415
21.1.2 Block parts...................................................................................................................................................416
21.1.3 Features........................................................................................................................................................418
21.2 Modes of operation.......................................................................................................................................................419
21.3 Memory map/register definition...................................................................................................................................419
21.3.1 Control Register (DMA_CR).......................................................................................................................434
21.3.2 Error Status Register (DMA_ES)................................................................................................................436
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................438
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................440
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................442
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
16 Freescale Semiconductor, Inc.