Information

Table 53-3. 4-bit JTAG instructions (continued)
Instruction Code[3:0] Instruction Summary
ARM JTAG-DP Reserved 1011 This instruction goes the ARM JTAG-DP controller. See the
ARM JTAG-DP documentation for more information.
CLAMP 1100 Selects bypass register while applying preloaded values to
output pins and asserting functional reset
ARM JTAG-DP Reserved 1110 This instruction goes the ARM JTAG-DP controller. See the
ARM JTAG-DP documentation for more information.
BYPASS 1111 Selects bypass register for data operations
53.4.4.1 IDCODE instruction
IDCODE selects the 32-bit device identification register as the shift path between TDI
and TDO. This instruction allows interrogation of the MCU to determine its version
number and other part identification data. IDCODE is the instruction placed into the
instruction register when the JTAGC block is reset.
53.4.4.2 EZPORT instruction
The EZPORT instruction allows for the EZPORT module to program the on-chip flash
from a simple 4-pin interface. The JTAGC forces the core into a reset state and forces the
EZPORT mode select/chip select low. In this mode, the flash can be programmed
through the JTAG test port pins, which are connected to the EZPORT module.
53.4.4.3 SAMPLE/PRELOAD instruction
The SAMPLE/PRELOAD instruction has two functions:
• The SAMPLE portion of the instruction obtains a sample of the system data and
control signals present at the MCU input pins and just before the boundary scan
register cells at the output pins. This sampling occurs on the rising edge of TCK in
the Capture-DR state when the SAMPLE/PRELOAD instruction is active. The
sampled data is viewed by shifting it through the boundary scan register to the TDO
output during the Shift-DR state. Both the data capture and the shift operation are
transparent to system operation.
• The PRELOAD portion of the instruction initializes the boundary scan register cells
before selecting the EXTEST or CLAMP instructions to perform boundary scan
tests. This is achieved by shifting in initialization data to the boundary scan register
during the Shift-DR state. The initialization data is transferred to the parallel outputs
Functional description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
1606 Freescale Semiconductor, Inc.