Information

A.11 Signal Multiplexing and Signal Descriptions chapter
changes
• Updated pinout diagrams and tables
• In 'Port control and interrupt module features' section, updated digital filter clock cycles from 1 to 32.
• Updated CMPx_IN signals to 5:0.
• In 'System Signal Descriptions' table, modified RESET_b pin to I/O.
• For the "Signal Multiplexing and Pin Assignments" table, added the LLWU inputs to the appropriate pin names.
A.12 PORT changes
• No substantial content changes
A.13 SIM changes
• Updated ADCxTRGSEL, PFSIZE, and EESIZE field descriptions.
A.14 Mode Controller changes
• In Modes of Operation section, updated VLPR mode description in Power modes table.
• Clarified Very Low Power Run (VLPR) Mode section.
A.15 PMC changes
• No substantial content changes
A.16 LLWU changes
• No substantial content changes
A.17 MCM changes
• No substantial content changes
Appendix A Release Notes for Revision 6
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 1611