Information

OSC MCG SIM
Muliplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2
Dividers — MCG_Cx SIM_CLKDIVx
Clock gates OSC_CR MCG_C1 SIM_SCGCx
32 kHz IRC
PLL
FLL
MCGOUTCLK
MCGPLLCLK
MCG
MCGFLLCLK
OUTDIV1
Core / system clocks
4 MHz IRC
OUTDIV4
Flash clock
Real-time clock
OUTDIV2
Bus clock
RTC oscillator
EXTAL32
XTAL32
EXTAL
XTAL
System oscillator
SIM
FRDIV
MCGIRCLK
ERCLK32K
OSC32KCLK
XTAL_CLK
÷2
MCGFFCLK
OSCERCLK
OSC
logic
OSC logic
Clock options for some
peripherals (see note)
Clock options for
some peripherals
(see note)
MCGFLLCLK
MCGPLLCLK/
Note: See subsequent sections for details on where these clocks are used.
PMC logic
PMC
LPO
OSCCLK
CG
CG
CG
CG
CG
CG — Clock gate
÷2
OUTDIV3
FlexBus clock
CG
Figure 5-1. Clocking diagram
5.4 Clock definitions
The following table describes the clocks in the previous block diagram.
Clock name Description
Core clock MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex-
M4 core
System clock MCGOUTCLK divided by OUTDIV1 clocks the crossbar
switch and bus masters directly connected to the crossbar. In
addition, this clock is used for UART0 and UART1.
Table continues on the next page...
Clock definitions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
168 Freescale Semiconductor, Inc.