Information

5.7.9 SDHC clocking
The SDHC module has four possible clock sources for the external clock source, as
shown in the following figure.
SIM_SOPT2[SDHCSRC]
SDHC clock
MCGPLLCLK or
MCGFLLCLK
Core / system clock
OSCERCLK
SDHC0_CLKIN
Figure 5-8. SDHC clock generation
5.7.10 I
2
S clocking
In addition to the bus clock, the I
2
S has a clock source for master clock generation. The
maximum frequency of this clock is 50 MHz. The master clock source can be derived
from several sources, as shown in the following figure.
SIM_SOPT2[I2SSRC]
Core/system clock
MCGPLLCLK or
MCGFLLCLK
OSCERCLK
S master clockI
2
I2S_CLKIN
SIM_CLKDIV2
[I2SFRAC,I2SDIV]
Figure 5-9. I
2
S baud clock generation
5.7.11 TSI clocking
In active mode, the TSI can be clocked as shown in the following figure.
Module clocks
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
178 Freescale Semiconductor, Inc.