Information

Table 7-2. Module operation in low power modes (continued)

Modules Stop VLPR VLPW VLPS LLS VLLSx

TSI wakeup FF FF wakeup wakeup

wakeup

1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be

enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a

transition to occur to the LLWU.

2. A 4KB portion of SRAM_U block is left powered on in low power mode VLLS2.

3. These components remain powered in BAT power mode.

4. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL).

5. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS

or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered

modes of operation are not available while in stop, VLPS, LLS, or VLLSx modes.

6. TSI wakeup from LLS and VLLSx modes is limited to a single selectable pin.

7.7 Clock Gating

To conserve power, the clocks to most modules can be turned off using the SCGCx

registers in the SIM module. These bits are cleared after any reset, which disables the

clock to the corresponding module. Prior to initializing a module, set the corresponding

bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to

disable the module. For more details, refer to the clock distribution and SIM chapters.

Clock Gating

K20 Sub-Family Reference Manual, Rev. 6, Nov 2011

198 Freescale Semiconductor, Inc.