Information

Table 9-1. Debug Components Description (continued)
Module Description
DWT (Data and Address Watchpoints) 4 data and address watchpoints (configurable for less, but 4
seems to be accepted)
FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches
code and data from code space to system space.
The FPB unit contains two literal comparators for matching
against literal loads from Code space, and remapping to a
corresponding area in System space.
The FBP also contains six instruction comparators for
matching against instruction fetches from Code space, and
remapping to a corresponding area in System space.
Alternatively, the six instruction comparators can individually
configure the comparators to return a Breakpoint Instruction
(BKPT) to the processor core on a match, so providing
hardware breakpoint capability.
TPIU (Trace Port Inteface Unit) Synchronous Mode (5-pin) = TRACE_D[3:0] +
TRACE_CLKOUT
Synchronous Mode (3-pin) = TRACE_D[1:0] +
TRACE_CLKOUT
Asynchronous Mode (1-pin) = TRACE_SWO (available on
JTAG_TDO)
MCM (Miscellaneous Control Module) The MCM provides miscellaneous control functions including
control of the ETB and trace path switching.
9.1.1 References
For more information on ARM debug components, see these documents:
• ARMv7-M Architecture Reference Manual
• ARM Debug Interface v5.1
• ARM CoreSight Architecture Specification
• ARM ETM Architecture Specification v3.5
9.2 The Debug Port
The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in
the following figure:
Chapter 9 Debug
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 205