Information

10.3.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
The 81-pin ballmap assignments are currently being developed.
The • in the entries in this package column indicate which
signals are present on the package.
81
MAP
BGA
80
LQF
P
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E4 1 PTE0 ADC1_SE4
a
ADC1_SE4
a
PTE0 SPI1_PCS1 UART1_TX SDHC0_D1 I2C1_SDA
E3 2 PTE1/
LLWU_P0
ADC1_SE5
a
ADC1_SE5
a
PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL
E2 3 PTE2/
LLWU_P1
ADC1_SE6
a
ADC1_SE6
a
PTE2/
LLWU_P1
SPI1_SCK UART1_CT
S_b
SDHC0_DC
LK
F4 4 PTE3 ADC1_SE7
a
ADC1_SE7
a
PTE3 SPI1_SIN UART1_RT
S_b
SDHC0_CM
D
E7 — VDD VDD VDD
F7 — VSS VSS VSS
H7 5 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
G4 6 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2
E6 7 VDD VDD VDD
G7 8 VSS VSS VSS
L6 — VSS VSS VSS
F1 9 USB0_DP USB0_DP USB0_DP
F2 10 USB0_DM USB0_DM USB0_DM
G1 11 VOUT33 VOUT33 VOUT33
G2 12 VREGIN VREGIN VREGIN
K1 13 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
K2 14 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
L1 15 PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
L2 16 PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 221