Information

81
MAP
BGA
80
LQF
P
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
F5 17 VDDA VDDA VDDA
G5 18 VREFH VREFH VREFH
G6 19 VREFL VREFL VREFL
F6 20 VSSA VSSA VSSA
L3 21 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE1
8
K5 22 DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
DAC0_OUT/
CMP1_IN3/
ADC0_SE2
3
L4 23 XTAL32 XTAL32 XTAL32
L5 24 EXTAL32 EXTAL32 EXTAL32
K6 25 VBAT VBAT VBAT
J6 26 PTA0 JTAG_TCL
K/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CT
S_b
FTM0_CH5 JTAG_TCL
K/
SWD_CLK
EZP_CLK
H8 27 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
J7 28 PTA2 JTAG_TDO/
TRACE_SW
O/EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SW
O
EZP_DO
H9 29 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RT
S_b
FTM0_CH0 JTAG_TMS/
SWD_DIO
J8 30 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
K7 31 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUT I2S0_RX_B
CLK
JTAG_TRS
T
E5 — VDD VDD VDD
G3 — VSS VSS VSS
K8 32 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_
PHA
L8 33 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 I2S0_TX_F
S
FTM1_QD_
PHB
K9 34 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_TX_B
CLK
L9 35 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD
J10 36 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CT
S_b
I2S0_RX_F
S
H10 37 PTA17 ADC1_SE1
7
ADC1_SE1
7
PTA17 SPI0_SIN UART0_RT
S_b
I2S0_MCLK I2S0_CLKIN
L10 38 VDD VDD VDD
K10 39 VSS VSS VSS
Pinout
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
222 Freescale Semiconductor, Inc.