Information

81
MAP
BGA
80
LQF
P
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
L11 40 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN
0
K11 41 PTA19 XTAL XTAL PTA19 FTM1_FLT0 FTM_CLKIN
1
LPT0_ALT1
J11 42 RESET_b RESET_b RESET_b
G11 43 PTB0/
LLWU_P5
/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
G10 44 PTB1 /
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
/
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
G9 45 PTB2 /
ADC0_SE1
2/TSI0_CH7
/
ADC0_SE1
2/TSI0_CH7
PTB2 I2C0_SCL UART0_RT
S_b
FTM0_FLT3
G8 46 PTB3 /
ADC0_SE1
3/TSI0_CH8
/
ADC0_SE1
3/TSI0_CH8
PTB3 I2C0_SDA UART0_CT
S_b
FTM0_FLT0
D10 47 PTB10 /
ADC1_SE1
4
/
ADC1_SE1
4
PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1
C10 48 PTB11 /
ADC1_SE1
5
/
ADC1_SE1
5
PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2
— 49 VSS VSS VSS
— 50 VDD VDD VDD
B10 51 PTB16 /TSI0_CH9 /TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN
E9 52 PTB17 /TSI0_CH10 /TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT
_b
D9 53 PTB18 /TSI0_CH11 /TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 I2S0_TX_B
CLK
FB_AD15 FTM2_QD_
PHA
C9 54 PTB19 /TSI0_CH12 /TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 I2S0_TX_F
S
FB_OE_b FTM2_QD_
PHB
B9 55 PTC0 /
ADC0_SE1
4/
TSI0_CH13
/
ADC0_SE1
4/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXT
RG
I2S0_TXD FB_AD14
D8 56 PTC1/
LLWU_P6
/
ADC0_SE1
5/
TSI0_CH14
/
ADC0_SE1
5/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RT
S_b
FTM0_CH0 FB_AD13
C8 57 PTC2 /
ADC0_SE4
b/
CMP1_IN0/
TSI0_CH15
/
ADC0_SE4
b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CT
S_b
FTM0_CH1 FB_AD12
B8 58 PTC3/
LLWU_P7
/CMP1_IN1 /CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 FB_CLKOU
T
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 223