Information

Table 10-17. TRIAMP 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
TRI1_DP inp_3v Amplifier positive input terminal I
TRI1_DM inn_3v Amplifier negative input terminal I
TRI1_OUT out_3v Amplifier output terminal O
Table 10-18. VREF Signal Descriptions
Chip signal name Module signal
name
Description I/O
VREF_OUT VREF_OUT Internally-generated Voltage Reference output O
10.4.6 Communication Interfaces
Table 10-19. USB FS OTG Signal Descriptions
Chip signal name Module signal
name
Description I/O
USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O
USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O
USB_CLKIN — Alternate USB clock input I
Table 10-20. USB VREG Signal Descriptions
Chip signal name Module signal
name
Description I/O
VOUT33 reg33_out Regulator output voltage O
VREGIN reg33_in Unregulated power supply I
Table 10-21. CAN 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CAN0_RX CAN Rx CAN Receive Pin Input
CAN0_TX CAN Tx CAN Transmit Pin Output
Table 10-22. CAN 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CAN1_RX CAN Rx CAN Receive Pin Input
CAN1_TX CAN Tx CAN Transmit Pin Output
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 233