Information

Table 10-23. SPI 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
SPI0_PCS0 PCS0/SS Master mode: Peripheral Chip Select 0 output
Slave mode: Slave Select input
I/O
SPI0_PCS[3:1] PCS[3:1] Master mode: Peripheral Chip Select 1 - 3
Slave mode: Unused
O
SPI0_PCS4 PCS4 Master mode: Peripheral Chip Select 4
Slave mode: Unused
O
SPI0_PCS5 PCS5/ PCSS Master mode: Peripheral Chip Select 5 /
Peripheral Chip Select Strobe
Slave mode: Unused
O
SPI0_SIN SIN Serial Data In I
SPI0_SOUT SOUT Serial Data Out O
SPI0_SCK SCK Master mode: Serial Clock (output)
Slave mode: Serial Clock (input)
I/O
Table 10-24. I
2
C 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
I2C0_SCL SCL Bidirectional serial clock line of the I
2
C system. I/O
I2C0_SDA SDA Bidirectional serial data line of the I
2
C system. I/O
Table 10-25. I
2
C 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
I2C1_SCL SCL Bidirectional serial clock line of the I
2
C system. I/O
I2C1_SDA SDA Bidirectional serial data line of the I
2
C system. I/O
Table 10-26. UART 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
UART0_CTS CTS Clear to send I
UART0_RTS RTS Request to send O
UART0_TX TXD Transmit data O
UART0_RX RXD Receive data I
Module Signal Description Tables
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
234 Freescale Semiconductor, Inc.